RecOnfigurable Computing and Systems Workshop 2026

About

Reconfigurable computing involves using hardware that can be dynamically reprogrammed to optimize performance for specific tasks. Field-Programmable Gate Arrays (FPGAs) are mainly used for reconfigurable computing, and are crucial for high-performance computing applications and for accelerating machine learning (ML) workloads. Unlike general-purpose CPUs and GPUs, FPGAs can be reconfigured to execute repetitive and computationally intense operations, offering better energy efficiency.

The Reconfigurable Computing and Systems Workshop (ROCS 2026) is the third edition of the ROCS series, held previously at HiPC 2024 and HiPC 2025, and returns to HiPC 2026 in Bengaluru. Reconfigurable architectures offer compelling solutions to the computational patterns arising in deep learning, genomics, computational physics, drug discovery, and beyond, owing to their adaptability and customizability. Unlike GPUs, however, FPGAs have yet to become widely usable general-purpose accelerators. ROCS 2026 asks whether FPGAs are now positioned to offer viable alternatives where cost, power, and performance align, and whether recent advances in agentic AI can make HLS and design tools more capable and accessible.

Building on a growing community, this year the workshop introduces a peer-reviewed short-paper track, alongside a poster-abstract track, invited talks, and industry sessions.

Call for Papers

Themes

The 2026 edition sharpens its focus around three themes:

• Application-level acceleration using heterogeneous FPGAs
• AI/ML on FPGAs
• LLM/agent-driven tooling for rapid FPGA development

Topics of Interest

We invite submissions on topics including, but not limited to:

• FPGA and reconfigurable architectures; adaptive and heterogeneous compute (e.g., Versal-class devices)
• High-Level Synthesis (HLS), EDA tooling, and design automation for FPGAs
• Agentic AI and LLMs for hardware generation, optimization, verification, and design-space exploration
• AI/ML acceleration on FPGAs: deep learning, CNNs, transformer and LLM inference
• Domain acceleration on reconfigurable hardware: genomics, computational physics, drug discovery, graph analytics, and scientific computing
• Runtime reconfiguration, adaptive systems, and reconfigurable systems software
• Performance, power, and cost efficiency studies comparing FPGAs with GPUs and other accelerators
• Programming models, frameworks, and toolchains that lower the barrier to FPGA development
• Case studies, reproducibility, and lessons learned in deploying reconfigurable systems

Important Dates

Deadlines follow the HiPC 2026 workshop proceedings schedule. The camera-ready deadline is firm, as it is set by the conference proceedings timeline.

Submission Guidelines

ROCS 2026 solicits submissions in two tracks, both relevant to the workshop themes:

• 1. Short papers — original work, work in progress, or experience/position contributions.
  Length: up to 4 pages excluding references (figures included in the 4-page count; references may spill onto additional pages).
  Format: IEEE conference template, two-column, 10pt.
• 2. Poster abstracts — early-stage results, student work, and preliminary ideas.
  Length: up to 2 pages including references.
  Format: IEEE conference template, two-column, 10pt.

Common Guidelines

• Review: each submission is peer-reviewed by at least three program-committee members. Reviewing is single-blind. Selection is based on technical quality, relevance to the workshop theme, and potential to spark discussion.
• Presentation: accepted short papers will be presented as talks; accepted poster abstracts will be presented as lightning talks and posters.
• In-person presentation required: every accepted contribution must be presented in person by one of its authors. Virtual presentations are not permitted.
• Registration: each accepted paper must be covered by a full registration for the main HiPC 2026 conference.
• Publication: accepted short papers will be included in the HiPC Workshops (HiPCW 2026) proceedings, a dedicated volume with its own ISBN; eligible papers are also submitted to the IEEE Xplore Digital Library after the conference. Authors who prefer not to publish may opt out at the camera-ready stage and present their work at the workshop only, retaining full freedom to submit extended versions elsewhere. Poster abstracts are presentation-only and do not appear in the proceedings.
• Submission site: all submissions are made through Linklings, the HiPC submission system. Link to be announced here.

Program

ROCS 2026 is a half-day workshop combining invited talks, peer-reviewed short contributions, and industry engagement, comprising an invited keynote, presentations of accepted short papers, lightning talks and posters, and industry technical talks.

Keynote & Invited Speakers

Keynote and invited speakers are being confirmed and will be announced here. The program will feature an invited keynote, invited talks, and industry technical talks.

Organizers

• Suresh Purini — Associate Professor, IIIT Hyderabad
• Chandan Karfa — Associate Professor, IIT Guwahati
• Madhura Purnaprajna — AMD, Bengaluru
• Jayashree H V — AMD University Program

Names link to email.

Program Committee

• Chandan Karfa — IIT Guwahati
• Shashwat Khandelwal — Arm, Cambridge
• Rajesh Kedia — IIT Hyderabad
• Suresh Purini — IIIT Hyderabad
• Madhura Purnaprajna — AMD, Bengaluru
• Shashwat Shrivastava — EPFL
• Kizheppatt Vipin — BITS Pilani, Goa

Additional members to be announced.

Registration & Contact

Registration is handled through the HiPC registration page at https://hipc.org/attendee-registration/

For inquiries, please email: rocs.hipc@gmail.com

Previous editions: ROCS 2025