RecOnfigurable Computing and Systems Workshop 2025

About

Reconfigurable computing involves using hardware that can be dynamically reprogrammed to optimize performance for specific tasks. Field-Programmable Gate Arrays (FPGAs) are mainly used for reconfigurable computing, and are crucial for high-performance computing applications and accelerating machine learning (ML) applications. Unlike general-purpose CPUs and GPUs, FPGAs can be reconfigured to execute repetitive and computationally intense operations, offering better energy efficiency. The Reconfigurable Computing and Systems Workshop (ROCS) is aimed at attracting participants to discuss architecture of latest FPGAs and flows for executing deep learning workloads on such FPGA.

Keynote

• Keynote Speaker: Avra Chatterjee
• Title: FPGAs for Deep Learning

Speaker Bio: Avra Chatterjee is the Senior Director of Software Development at AMD, where Avra leads the verification of all products within the Adaptive and Embedded Computing Group (AECG) Business Unit. With over 25 years of experience at AMD and formerly Xilinx, Avra has been instrumental in shaping the verification strategy and execution across generations of cutting-edge technologies. Avra holds a B.Tech in Electrical Engineering from the Indian Institute of Technology, Kharagpur, and a Master’s in Electrical Engineering from San Jose State University.

Tutorials

• AMD Versal Device and Vitis Flow
  Presenter: Wikneswaran (Wicky) Pillai, AMD
  Bio: TBD
  
  

  This tutorial introduces AMD Versal as an adaptable and heterogeneous compute platform, while relating to the generic compute architectures. The benefits of the micro-architectures of Programmable Logic and AI Engine as high-throughput accelerators will be discussed. Finally, an overview of the compile, link and build flows will be presented.

• Executing CNNs on AMD DPUs
  Presenters: M A Muneeb and Rajesh Kedia, IIT Hyderabad
  Bio: M A Muneeb is an M.Tech. (research) student in CSE at IIT Hyderabad.
  Rajesh Kedia is an assistant professor of CSE at IIT Hyderabad.
  
  

  This tutorial will cover our flows and methodology for executing various CNNs on Deep learning Processor Unit (DPU) which is a CNN accelerator for FPGAs. The tutorial will also expose the participants to Heterogeneous Accelerated Compute Cluster (HACC).

• AI on AMD NPUs
  Presenters: Naveen Purushotham, AMD
  Bio: Naveen Purushotham is a Member of the Technical Staff at AMD University Program, part of AMD Research and Advanced Development, in San Jose, CA, where he works with academic institutions on teaching and research initiatives. His recent focus has been on Efficient and Applied Deep Learning for AMD AI products. Before joining AMD through its acquisition of Xilinx, he worked at Lattice Semiconductor as a Product Engineer in semiconductor product development. He holds an M.S. in Electrical and Computer Engineering from the University of New Mexico and a Master of Information and Data Science from the University of California, Berkeley.

  
  This tutorial introduces the AMD AI PC ecosystem, focusing on how the Neural Processing Unit (NPU) enables efficient AI workloads. The session explores the practical advantages of NPUs in boosting performance while minimizing energy consumption. Students will gain hands-on experience with the Ryzen AI software stack, using tools such as Quark Quantizer and ONNX Runtime to deploy AI models effectively. We will also discuss quantization - a key technique that optimizes model performance by reducing computation costs and memory usage while maintaining accuracy. The tutorial concludes with a demonstration of computer vision model deployment on the Ryzen™ AI PC, comparing performance across CPU, iGPU, and NPU platforms.

Schedule

Organizers

• Madhura Purnaprajna
  Affiliation: AMD and PES University, Bengaluru
  Bio: Madhura Purnaprajna is currently at AMD (Xilinx), where she looks at performance projections for next-gen AMD (Xilinx) ACAP devices. She received her Ph.D. in electrical engineering from the Heinz Nixdorf Institute, University of Paderborn, Germany. She was a Postdoctoral Fellow with an International Research Fellowship from the German Research Foundation (Deutsche Forschungsgemenischaft) and MHV Fellowship (SNSF), at the Processor Architecture Lab, EPFL, Switzerland, and the High-performance Computing Lab, Indian Institute of Science Bengaluru, Bengaluru. She is currently on a sabbatical from PES University.
• Rajesh Kedia
  Affiliation: IIT Hyderabad
  Bio: Rajesh Kedia is an assistant professor of CSE at IIT Hyderabad, with expertise in reconfigurable computing, FPGA design, and embedded AI systems.
• Naveen Purushotham
  Affiliation: AMD University Program
  Bio: Naveen Purushotham is a Member of the Technical Staff at AMD University Program, part of AMD Research and Advanced Development, in San Jose, CA, where he works with academic institutions on teaching and research initiatives. His recent focus has been on Efficient and Applied Deep Learning for AMD AI products. Before joining AMD through its acquisition of Xilinx, he worked at Lattice Semiconductor as a Product Engineer in semiconductor product development. He holds an M.S. in Electrical and Computer Engineering from the University of New Mexico and a Master of Information and Data Science from the University of California, Berkeley.
• Andrew Schmidt
  Affiliation: AMD University Program
  Bio: Dr. Andrew Schmidt is a passionate advocate for advancing technology education and research, with a rich background in academia and industry. Andrew leverages his expertise to drive innovation and collaboration within the academic community. In this role, Andrew works closely with university faculty, researchers, and students to promote the adoption of AMD technologies in academic research and curriculum development through workshops, tutorials, and collaborative projects.  Andrew received his B.S. and M.S. in Computer Engineering from the University of Kansas and his Ph.D. in Electrical Engineering from the University of North Carolina at Charlotte.

Contact

For inquiries, please email: rocs.hipc@gmail.com